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DATA SHEET
MOS INTEGRATED CIRCUIT
PD720101
USB2.0 HOST CONTROLLER
The PD720101 complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for high-speed signaling and works up to 480 Mbps. The PD720101 is integrated 3 host controller cores with PCI interface and USB2.0 transceivers into a single chip. Detailed function descriptions are provided in the following user's manual. Be sure to read the manual before designing.
PD720101 User's Manual: S16336E
FEATURES
* Compliant with Universal Serial Bus Specification Revision 2.0 (Data rate 1.5/12/480 Mbps) * Compliant with Open Host Controller Interface Specification for USB Rev 1.0a * Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0 * PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host controller core for high-speed signaling. * Root hub with 5 (max.) downstream facing ports which are shared by OHCI and EHCI host controller cores. * All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction. * Configurable number of downstream facing ports (2 to 5) * 32-bit 33 MHz host interface compliant to PCI Specification release 2.2 * Supports PCI Mobile Design Guide Revision 1.1 * Supports PCI-Bus Power Management Interface Specification release 1.1 * PCI bus bus-master access * System clock is generated by 30 MHz X'tal or 48 MHz clock input. - System clock frequency should be set from system software (BIOS) or EEPROM. More detail, see PD720101 User's Manual. * Operational registers direct-mapped to PCI memory space * Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard implementation. * 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.
ORDERING INFORMATION
Part Number Package 144-pin plastic LQFP (Fine pitch) (20 x 20) 144-pin plastic FBGA (12 x 12)
PD720101GJ-UEN PD720101F1-EA8
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
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Document No. S16265EJ4V0DS00 (4th edition) Date Published June 2004 NS CP (N) Printed in Japan
The mark
shows major revised points.
2002
PD720101
BLOCK DIAGRAM
PCI Bus
PME0 INTA0 INTB0 INTC0
PCI Bus Interface
WakeUp_Event WakeUp_Event WakeUp_Event
Arbiter
OHCI Host Controller #1
OHCI Host Controller #2
EHCI Host Controller
SMI0
Root Hub
PHY
Port 1 Port 2 Port 3 Port 4 Port 5
USB Bus
Remark INTB0/INTC0 can be shared with INTA0 through BIOS setting. (Planning)
2
Data Sheet S16265EJ4V0DS
PD720101
PCI Bus Interface : handles 32-bit 33 MHz PCI bus master and target function which comply with PCI specification release 2.2. The number of enabled ports is set by bit in configuration space. Arbiter OHCI Host Controller #1 OHCI Host Controller #2 EHCI Host Controller Root Hub PHY INTA0 INTB0 INTC0 SMI0 : arbitrates among two OHCI host controller cores and one EHCI host controller core. : handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 1, 3, and 5. : handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 2 and 4. : handles high- (480 Mbps) signaling at port 1, 2, 3, 4, and 5. : handles USB hub function in host controller and controls connection (routing) between host controller core and port. : consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer, etc. : is the PCI interrupt signal for OHCI Host Controller #1. : is the PCI interrupt signal for OHCI Host Controller #2. : is the PCI interrupt signal for EHCI Host Controller. : is the interrupt signal which is specified by Open Host Controller Interface Specification for USB Rev 1.0a and Enhanced Host Controller Interface Specification Rev 1.0. The SMI signal of each OHCI Host Controller and EHCI Host Controller appears at this signal. PME0 : is the interrupt signal which is specified by PCI-Bus Power Management Interface Specification release 1.1. Wakeup signal of each host controller core appears at this signal.
COMPARISON WITH THE PD720100A
PD720100A
EHCI revision EHCI OHCI Legacy support Clock Package 0.95 1 2 Parallel IRQ out support 48 MHz OSC or 30 MHz OSC/X'tal 176-pin BGA (FP) or 160-pin LQFP 1.0 1 2 No parallel IRQ support 48 MHz OSC or 30 MHz X'tal 144-pin BGA (FP) or 144-pin LQFP
PD720101 (2nd generation)
Data Sheet S16265EJ4V0DS
3
PD720101
PIN CONFIGURATION
* 144-pin plastic LQFP (Fine pitch) (20 x 20)
PD720101GJ-UEN
Top View
VSS VSS RSDP5 DP5 VDD DM5 RSDM5 VSS RSDP4 DP4 VDD DM4 RSDM4 VSS RSDP3 DP3 VDD DM3 RSDM3 VSS VDD VSS VSS RSDP2 DP2 VDD DM2 RSDM2 VSS RSDP1 DP1 VDD DM1 RSDM1 VSS VSS 135 144 125 115 140
VDD VDD OCI1 PPON1 OCI2 PPON2 OCI3 PPON3 OCI4 PPON4 OCI5 PPON5 VCCRST0 PME0 PCLK VBBRST0 VDD_PCI VSS VDD INTA0 INTB0 INTC0 GNT0 REQ0 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 CBE30 IDSEL VSS VDD
130
120
110
1
105 5
100 10
95 15
90 20
85 25
80 30
75 35
60
65
40
45
4
VSS VSS AD23 AD22 AD21 AD20 VDD AD19 AD18 AD17 AD16 CBE20 FRAME0 IRDY0 TRDY0 DEVSEL0 STOP0 VSS VDD VDD_PCI PERR0 SERR0 PAR CBE10 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 CBE00 AD7 VSS VSS
Data Sheet S16265EJ4V0DS
50
55
70
VDD AVSS AVDD AVSS AVSS(R) RREF AVDD VSS VSS NANDTEST SRDTA SRMOD SRCLK XT1/SCLK XT2 VDD NTEST1 TEST LEGC SMC TEB AMC SMI0 N.C. N.C. CRUN0 AD0 AD1 VDD_PCI AD2 AD3 AD4 AD5 AD6 VDD VDD
PD720101
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name VDD VDD OCI1 PPON1 OCI2 PPON2 OCI3 PPON3 OCI4 PPON4 OCI5 PPON5 VCCRST0 PME0 PCLK VBBRST0 VDD_PCI VSS VDD INTA0 INTB0 INTC0 GNT0 REQ0 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 CBE30 IDSEL VSS VDD Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name VSS VSS AD23 AD22 AD21 AD20 VDD AD19 AD18 AD17 AD16 CBE20 FRAME0 IRDY0 TRDY0 DEVSEL0 STOP0 VSS VDD VDD_PCI PERR0 SERR0 PAR CBE10 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 CBE00 AD7 VSS VSS Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin Name VDD VDD AD6 AD5 AD4 AD3 AD2 VDD_PCI AD1 AD0 CRUN0 N.C. N.C. SMI0 AMC TEB SMC LEGC TEST NTEST1 VDD XT2 XT1/SCLK SRCLK SRMOD SRDTA NANDTEST VSS VSS AVDD RREF AVSS(R) AVSS AVDD AVSS VDD Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin Name VSS VSS RSDM1 DM1 VDD DP1 RSDP1 VSS RSDM2 DM2 VDD DP2 RSDP2 VSS VSS VDD VSS RSDM3 DM3 VDD DP3 RSDP3 VSS RSDM4 DM4 VDD DP4 RSDP4 VSS RSDM5 DM5 VDD DP5 RSDP5 VSS VSS
Remark AVSS(R) should be used to connect RREF through 1 % precision reference resistor of 9.1 k. Pins 84 and 85 must be clamped high on the board.
Data Sheet S16265EJ4V0DS
5
PD720101
* 144-pin plastic FBGA (12 x 12)
PD720101F1-EA8
Bottom View
25 24 23 22 21 20 19 18 17 16 15 14 13 71 70 69 68 67 66 65 64 63 62 61 60 12 P N 26 72 111 110 109 108 107 106 105 104 103 102 59 11 M 101 58 10 L 100 57 9 K 132 99 56 8 J 131 98 55 7 H 130 97 54 6 G 129 96 53 5 F 95 52 4 E 94 51 3 D 136 135 134 133 141 142 143 144 27 73 112 28 74 113 29 75 114 137 30 76 115 138 31 77 116 139 32 78 117 140 33 79 118 34 80 119 35 81 120 121 122 123 124 125 126 127 128 93 50 2 C 36 82 83 84 85 86 87 88 89 90 91 92 49 1 B A 37 38 39 40 41 42 43 44 45 46 47 48 14 13 12 11 10 9 8 7 6 5 4 3 2 1
6
Data Sheet S16265EJ4V0DS
PD720101
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name VSS AD23 AD20 AD18 CBE20 TRDY0 SERR0 AD15 AD12 AD9 AD7 VSS VDD VDD AD3 AD1 N.C. AMC XT2 SRMOD VSS RREF VDD AVSS VSS RSDM1 DP1 RSDM2 DP2 VSS RSDP3 DM4 RSDP4 DM5 RSDP5 VSS Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name VDD VDD PPON2 OCI4 PPON5 PCLK INTC0 AD31 AD28 AD25 VDD VSS VSS AD22 AD21 VDD AD16 DEVSEL0 PERR0 AD14 AD10 AD8 CBE00 VSS AD6 AD4 AD2 CRUN0 TEB VDD SRDTA AVDD AVSS(R) AVDD VSS DM1 Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin Name VDD RSDP1 VDD VDD DP3 VDD RSDM5 VDD DP5 VSS OCI1 OCI2 OCI3 OCI5 VBBRST0 INTB0 AD30 AD26 AD24 IDSEL CBE30 AD19 AD17 FRAME0 STOP0 VDD_PCI CBE10 AD13 AD11 AD5 VDD_PCI AD0 N.C. SMC NTEST1 SRCLK Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin Name NANDTEST VSS AVSS VSS DM2 RSDP2 VSS VDD RSDM4 DP4 VSS PPON1 PPON3 PPON4 VCCRST0 VDD_PCI INTA0 REQ0 AD29 AD27 IRDY0 VSS VDD PAR SMI0 LEGC TEST XT1/SCLK VSS RSDM3 DM3 VSS PME0 VSS VDD GNT0
Remark AVSS(R) should be used to connect RREF through 1 % precision reference resistor of 9.1 k. Pins 17 and 105 must be clamped high on the board.
Data Sheet S16265EJ4V0DS
7
PD720101
1. PIN INFORMATION
(1/2)
Pin Name I/O Buffer Type Active Level AD (31 : 0) CBE (3 : 0)0 PAR FRAME0 IRDY0 TRDY0 STOP0 IDSEL DEVSEL0 REQ0 GNT0 PERR0 SERR0 INTA0 INTB0 INTC0 PCLK VBBRST0 CRUN0 PME0 VCCRST0 SMI0 XT1/SCLK XT2 DP (5 : 1) DM (5 : 1) RSDP (5 : 1) RSDM (5 : 1) OCI (5 : 1) PPON (5 : 1) LEGC SRCLK SRDTA SRMOD RREF NTEST1 I/O I/O I/O I/O I/O I/O I/O I I/O O I I/O O O O O I I I/O O I O I O I/O I/O O O I (I/O) O (I/O) I (I/O) O I/O I A I 5 V PCI I/O 5 V PCI I/O 5 V PCI I/O 5 V PCI I/O 5 V PCI I/O 5 V PCI I/O 5 V PCI I/O 5 V PCI input 5 V PCI I/O 5 V PCI output 5 V PCI input 5 V PCI I/O 5 V PCI N-ch open drain 5 V PCI N-ch open drain 5 V PCI N-ch open drain 5 V PCI N-ch open drain 5 V PCI input 5 V tolerant input 5 V PCI I/O 5 V PCI N-ch open drain 5 V tolerant input 5 V tolerant N-ch open drain Input Output USB high speed D+ I/O USB high speed D- I/O USB full speed D+ Output USB full speed D- Output Input Output Input Output I/O Input with 50 k pull down R Analog Input with 12 k pull down R High High Low High High Low Low Low Low Low Low Low PCI "AD [31 : 0]" signal PCI "C/BE [3 : 0]" signal PCI "PAR" signal PCI "FRAME#" signal PCI "IRDY#" signal PCI "TRDY#" signal PCI "STOP#" signal PCI "IDSEL" signal PCI "DEVSEL#" signal PCI "REQ#" signal PCI "GNT#" signal PCI "PERR#" signal PCI "SERR#" signal PCI "INTA#" signal PCI "INTB#" signal PCI "INTC#" signal PCI "CLK" signal Hardware reset for chip PCI "CLKRUN#" signal PCI "PME#" signal Reset for power management System management interrupt output System clock input or oscillator in oscillator out USB high speed D+ signal USB high speed D- signal USB full speed D+ signal USB full speed D- signal USB root hub port's overcurrent status input USB root hub port's power supply control output Legacy support switch Serial ROM clock out Serial ROM data Serial ROM input enable Reference resistor Test pin Function
8
Data Sheet S16265EJ4V0DS
PD720101
(2/2)
Pin Name I/O Buffer Type Active Level SMC TEB AMC TEST NANDTEST AVDD VDD VDD_PCI AVSS VSS N.C. I I I I I Input with 50 k pull down R Input with 50 k pull down R Input with 50 k pull down R Input with 50 k pull down R Input with 50 k pull down R High High High High High Scan mode control BIST enable ATG mode control Test control NAND tree test enable VDD for analog circuit VDD 5 V (5 V PCI) or 3.3 V (3.3 V PCI) VSS for analog circuit VSS No connection Function
Remarks 1. "5 V tolerant" means that the buffer is 3 V buffer with 5 V tolerant circuit. 2. "5 V PCI" indicates a PCI buffer, which complies with the 3 V PCI standard, has a 5 V tolerant circuit. It does not indicate that this buffer fully complies with 5 V PCI standard. However, this function can be used for evaluating the operation of a device on a 5 V add-in card. 3. The signal marked as "(I/O)" in the above table operates as I/O signals during testing. However, they do not need to be considered in normal use.
Data Sheet S16265EJ4V0DS
9
PD720101
2.
2.1
HOW TO CONNECT TO EXTERNAL ELEMENTS
Handling Unused Pins To realize less than 5 ports host controller implementation, appropriate value shall be set to Port No field in EXT1
register. And unused pins shall be connected as shown below.
Pin DPx DMx RSDPx RSDMx OCIx PPONx Direction I/O I/O O O I O Connection Method Tied to "low". Tied to "low". No connection (Open) No connection (Open) "H" clamp No connection (Open)
2.2
USB Port Connection Figure 2-1. USB Downstream Port Connection
Inside-package DP
Outside-package Port: D+
DM RS = 36 1% RSDP
Port: D-
RSDM RS = 36 1% RS + Ron (resistance for driver which is active) = 45 10% 15 k 5%
ground
10
Data Sheet S16265EJ4V0DS
PD720101
2.3 PLL Capacitor Connection Figure 2-2. RREF Connection
RREF
Inside-package
Outside-package 9.1 k 1%
AVSS(R)
2.4
X'tal Connection Figure 2-3. X'tal Connection
Inside-package
Outside-package
VSS C1 XT1/SCLK R XT2 C2 VSS X'tal
The following crystals are evaluated on our reference design board. Table 2-1 shows the external parameters.
Data Sheet S16265EJ4V0DS
11
PD720101
Table 2-1. External Parameters
Vender KDS NDK
Note 1 Note 2
X'tal AT-49 30.000 MHz AT-41 30.000 MHz AT-41CD2 30.000 MHz NX3225DA 30.000 MHz NX5032GA 30.000 MHz NX8045GB 30.000 MHz
R 100 100 100 100 100 100
C1 12 pF 10 pF 10 pF 10 pF 10 pF 10 pF
C2 10 pF 10 pF 10 pF 10 pF 10 pF 10 pF
Notes 1. DAISHINKU CORP. 2. NIHON DEMPA KOGYO CO., LTD. In using these crystals, contact KDS or NDK to get the specification on external components to be used in conjunction with the crystal. KDS's home page: http://www.kdsj.co.jp NDK's home page: http://www.ndk-j.co.jp 2.5 External Serial ROM Connection
Figure 2-4. External Serial ROM Connection
Inside-package
Outside-package
3.3 V
SRMOD
1.5 k C
External serial ROM VDD WP SCL A0 A1 A2
SRCLK SRDTA
SDA GND
These pins for external serial ROM can be opened, when serial ROM is not necessary on board.
12
Data Sheet S16265EJ4V0DS
PD720101
3.
3.1 * * * * * * * * * * *
ELECTRICAL SPECIFICATIONS
Buffer List
3 V input buffer with pull down resistor NTEST1, TEST, SRMOD, NANDTEST, SMC, AMC, TEB 3 V PCI IOL = 9 mA 3-state output buffer PPON(5:1), SRCLK 3 V IOL = 9 mA bi-directional buffer LEGC, SRDTA 3 V IOL = 9 mA bi-directional buffer with enable (OR type) OCI(5:1) 3 V oscillator interface XT1/SCLK, XT2 5 V input buffer VBBRST0, VCCRST0 5 V IOL = 12 mA N-ch open drain buffer SMI0, PME0, INTA0, INTB0, INTC0, SERR0 5 V PCI input buffer with enable (OR type) PCLK, GNT0, IDSEL 5 V PCI IOL = 12 mA 3-state output buffer REQ0 5 V PCI IOL = 9 mA bi-directional buffer with input enable (OR-type) AD(31:0), CBE(3:0)0, PAR, FRAME0, IRDY0, TRDY0, STOP0, DEVSEL0, PERR0, CRUN0 USB interface, analog signal DP(5:1), DM(5:1), RSDP(5:1), RSDM(5:1), RREF
Above, "5 V" refers to a 3 V buffer with 5 V tolerant circuit. Therefore, it is possible to have a 5 V connection for an external bus, but the output level will be only up to 3 V, which is the VDD voltage. Similarly, "5 V PCI" above refers to a PCI buffer that has a 5 V tolerant circuit, which meets the 3 V PCI standard; it does not refer to a PCI buffer that meets the 5 V PCI standard.
Data Sheet S16265EJ4V0DS
13
PD720101
3.2 Terminology
Terms Used in Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage Operating ambient temperature Storage temperature Symbol VDD, AVDD, VDD_PCI VI VO TA Tstg Meaning Indicates voltage range within which damage or reduced reliability will not result when power is applied to a VDD pin. Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Indicates the ambient temperature range for normal logic operations. Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device.
Terms Used in Recommended Operating Range
Parameter Power supply voltage High-level input voltage Symbol VDD, AVDD, VDD_PCI VIH Meaning Indicates the voltage range for normal logic operations occur when VSS = 0 V. Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * If a voltage that is equal to or greater than the "Min." value is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * If a voltage that is equal to or lesser than the "Max." value is applied, the input voltage is guaranteed as low level voltage.
Terms Used in DC Characteristics
Parameter Off-state output leakage current Output short circuit current Input leakage current Low-level output current High-level output current Symbol IOZ IOS II IOL IOH Meaning Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. Indicates the current that flows when the output pin is shorted (to GND pins) when output is at high-level. Indicates the current that flows when the input voltage is supplied to the input pin. Indicates the current that flows to the output pins when the rated low-level output voltage is being applied. Indicates the current that flows from the output pins when the rated highlevel output voltage is being applied.
14
Data Sheet S16265EJ4V0DS
PD720101
3.3 Electrical Specifications
Absolute Maximum Ratings
Parameter Power supply voltage Symbol VDD AVDD VDD_PCI Input voltage, 5 V buffer VI 3.0 V VDD 3.6 V VI < VDD + 3.0 V Input voltage, 3.3 V buffer VI 3.0 V VDD 3.6 V VI < VDD + 0.5 V Output voltage, 5 V buffer VO 3.0 V VDD 3.6 V VO < VDD + 3.0 V Output voltage, 3.3 V buffer VO 3.0 V VDD 3.6 V VO < VDD + 0.5 V Operating ambient temperature Storage temperature TA Tstg 0 to +70 -65 to +150 C C -0.5 to +4.6 V -0.5 to +6.6 V -0.5 to +4.6 V Condition Rating -0.5 to +4.6 -0.5 to +4.6 -0.5 to +6.0 -0.5 to +6.6 Unit V V V V
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Recommended Operating Ranges
Parameter Operating voltage Symbol VDD AVDD VDD_PCI In 3.3 V PCI In 5 V PCI High-level input voltage 3.3 V high-level input voltage 5.0 V high-level input voltage Low-level input voltage 3.3 V low-level input voltage 5.0 V low-level input voltage VIL 0 0 0.8 0.8 V V VIH 2.0 2.0 VDD 5.5 V V Condition Min. 3.0 3.0 3.0 4.75 Typ. 3.3 3.3 3.3 5.0 Max. 3.6 3.6 3.6 5.25 Unit V V V V
Data Sheet S16265EJ4V0DS
15
PD720101
DC Characteristics (VDD = 3.0 to 3.6 V, TA = 0 to +70C) Control pin block
Parameter Off-state output current Output short circuit current Low-level output current 3.3 V low-level output current 3.3 V low-level output current 5.0 V low-level output current 5.0 V low-level output current High-level output current 3.3 V high-level output current 3.3 V high-level output current 5.0 V high-level output current 5.0 V high-level output current Input leakage current 3.3 V buffer 3.3 V buffer with 50 k PD 5.0 V buffer II VI = VDD or VSS VI = VDD VI = VDD or VSS 10 191 10 IOH VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V -9.0 -3.0 -2.0 -2.0 mA mA mA mA Symbol IOZ IOS IOL VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V 9.0 3.0 12.0 6.0 mA mA mA mA
Note
Condition VO = VDD or VSS
Min.
Max. 10 -250
Unit
A
mA
A A A
Note The output short circuit time is one second or less and is only for one pin on the LSI. PCI interface block
Parameter High-level input voltage Low-level input voltage Low-level output current High-level output current Input high leakage current Input low leakage current PME0 leakage current Symbol VIH VIL IOL IOH IIH IIL IOFF VOL = 0.4 V VOH = 2.4 V VIN = 2.7 V VIN = 0.5 V VO < 3.6 V VCC off or floating Condition Min. 2.0 0 12.0 -2.0 70 -70 1 Max. 5.25 0.8 Unit V V mA mA
A A A
16
Data Sheet S16265EJ4V0DS
PD720101
USB interface block
Parameter Serial resistor between DP (DM) and RSDP (RSDM) Output pin impedance Input Levels for Low-/full-speed: High-level input voltage (drive) High-level input voltage (floating) Low-level input voltage Differential input sensitivity Differential common mode range Output Levels for Low-/full-speed: High-level output voltage Low-level output voltage SE1 Output signal crossover point voltage Input Levels for High-speed: High-speed squelch detection threshold (differential signal) High-speed disconnect detection threshold (differential signal) High-speed data signaling common mode voltage range High-speed differential input signaling level Output Levels for High-speed: High-speed idle state High-speed data signaling high High-speed data signaling low Chirp J level (differential signal) Chirp K level (differential signal) VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK -10 360 -10 700 -900 +10 440 +10 1100 -500 mV mV mV mV mV See Figure 3-4. VHSCM -50 +500 mV VHSDSC 525 625 mV VHSSQ 100 150 mV VOH VOL VOSE1 VCRS RL of 14.25 k to GND RL of 1.425 k to 3.6 V 2.8 0.0 0.8 1.3 2.0 3.6 0.3 V V V V VIH VIHZ VIL VDI VCM (D+) - (D-) Includes VDI range 0.2 0.8 2.5 2.0 2.7 3.6 0.8 V V V V V ZHSDRV Includes RS resistor 40.5 49.5 Symbol RS Conditions Min. 35.64 Max. 36.36 Unit
Data Sheet S16265EJ4V0DS
17
PD720101
Figure 3-1. Differential Input Sensitivity Range for Low-/full-speed
Differential Input Voltage Range Differential Output Crossover Voltage Range
-1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 4.6
Input Voltage Range (V)
Figure 3-2. Full-speed Buffer VOH/IOH Characteristics for High-speed Capable Transceiver
VDD-3.3 VDD-2.8 VDD-2.3 VDD-1.8 VDD-1.3 VDD-0.8 VDD-0.3 VDD 0
-20
IOUT (mA)
-40 Min. -60 Max. -80 VOUT (V)
Figure 3-3. Full-speed Buffer VOL/IOL Characteristics for High-speed Capable Transceiver
80 Max. 60 Min. 40
IOUT (mA)
20
0 0 0.5 1 1.5 VOUT (V) 2 2.5 3
18
Data Sheet S16265EJ4V0DS
PD720101
Figure 3-4. Receiver Sensitivity for Transceiver at DP/DM
Level 1
+400 mV Differential
Point 3
Point 4
Point 1
Point 2
0V Differential
Point 5
Point 6
Level 2
-400 mV Differential
0%
Unit Interval
100%
Figure 3-5. Receiver Measurement Fixtures
Test Supply Voltage 15.8 USB Connector Nearest Device Vbus D+ DGnd 50 Coax 50 Coax + To 50 Inputs of a High Speed Differential Oscilloscope, or 50 Outputs of a High Speed Differential Data Generator -
15.8
143
143
Pin capacitance
Parameter Input capacitance Output capacitance I/O capacitance PCI input pin capacitance PCI clock input pin capacitance PCI IDSEL input pin capacitance Symbol CI CO CIO Cin Cclk CIDSEL 6 Condition VDD = 0 V, TA = 25C fC = 1 MHz Unmeasured pins returned to 0 V 8 8 8 pF pF pF Min. 6 10 10 Max. 8 12 12 Unit pF pF pF
Data Sheet S16265EJ4V0DS
19
PD720101
Power consumption
Parameter Symbol Condition Typ. Typ. Unit
(30 MHz X'tal) (48 MHz OSC)
Power Consumption
PWD0-0
Device state = D0, All the ports does not connect to any function, and each OHCI controller is under Note1 UsbSuspend and EHCI controller is stopped.
31.4
10.4
mA
PWD0-2
The power consumption under the state without suspend. Device state = D0, The number of active Note2 ports is 2. Full- or low-speed device(s) is (are) on the port. High-speed device(s) is (are) on the port. 53.1 204.6 31.9 204.2 mA mA
PWD0-3
The power consumption under the state without suspend. Device state = D0, The number of active Note2 ports is 3. Full- or low-speed device(s) is (are) on the port. High-speed device(s) is (are) on the port. 55.3 253.8 34.2 255.5 mA mA
PWD0-4
The power consumption under the state without suspend. Device state = D0, The number of active Note2 ports is 4. Full- or low-speed device(s) is (are) on the port. High-speed device(s) is (are) on the port. 57.4 301.6 36.7 300.1 mA mA
PWD0-5
The power consumption under the state without suspend. Device state = D0, The number of active Note2 ports is 5. Full- or low-speed device(s) is (are) on the port. High-speed device(s) is (are) on the port. 59.8 349.1 30.5 7.7 7.7 7.7 0.03 38.8 345.2 10.4 10.4 10.4 10.4 3.81 mA mA mA mA mA mA mA
PWD0_C PWD1 PWD2 PWD3H PWD3C
The power consumption under suspend state during PCI clock is stopped by CRUN0. Device state = D0. Device state = D1, Analog PLL output is stopped. Device state = D2, Analog PLL output is stopped. output is stopped.
Note 3 Note 4 Note 3 Note 3
Device state = D3hot, VCCRST0 = High, Analog PLL Device state = D3cold, VCCRST0 = Low.
Notes 1. When any device is not connected to all the ports of HC, the power consumption for HC does not depend
on the number of active ports.
2. The number of active ports is set by the value of Port No Field in PCI configuration space EXT register. 3. This is the case when PCI bus state is B0. 4. This is the case when PCI bus state is B3. Remark These are estimated value on WindowsTM XP environment.
20
Data Sheet S16265EJ4V0DS
PD720101
System clock ratings
Parameter Clock frequency Symbol fCLK X'tal Oscillator block Clock duty cycle tDUTY Condition Min. -500 ppm -500 ppm 40 50 48 Typ. 30 Max. +500 ppm +500 ppm 60 % MHz Unit MHz
Remarks 1. Recommended accuracy of clock frequency is 100 ppm. 2. Required accuracy of X'tal or oscillator block is including initial frequency accuracy, the spread of X'tal
capacitor loading, supply voltage, temperature, and aging, etc.
Data Sheet S16265EJ4V0DS
21
PD720101
AC Characteristics (VDD = 3.0 to 3.6 V, TA = 0 to +70C) PCI interface block
Parameter PCI clock cycle time PCI clock pulse, high-level width PCI clock pulse, low-level width PCI clock, rise slew rate PCI clock, fall slew rate PCI reset active time (vs. power supply stability) PCI reset active time (vs. CLK start) Output float delay time (vs. RST0) PCI reset rise slew rate PCI bus signal output time (vs. PCLK) PCI point-to-point signal output time (vs. PCLK) Output delay time (vs. PCLK) Output float delay time (vs. PCLK) Input setup time (vs. PCLK) Point-to-point input setup time (vs. PCLK) Input hold time th 0 ns ton toff tsu tsu (ptp) GNT0 7 10 2 28 ns ns ns ns trst-clk trst-off Srr tval tval (ptp) REQ0 50 2 2 11 12 100 40 Symbol tcyc thigh tlow Scr Scf trst 0.2VDD to 0.6VDD 0.2VDD to 0.6VDD Condition Min. 30 11 11 1 1 1 4 4 Max. Unit ns ns ns V/ns V/ns ms
s
ns mV/ns ns ns
22
Data Sheet S16265EJ4V0DS
PD720101
USB interface block
(1/2)
Parameter Low-speed Source Electrical Characteristics Rise time (10 to 90%) Fall time (90 to 10%) Differential rise and fall time matching Low-speed data rate Source jitter total (including frequency tolerance): To next transition For paired transitions Source jitter for differential transition to SE0 transition Receiver jitter: To next transition For paired transitions Source SE0 interval of EOP Receiver SE0 interval of EOP Width of SE0 interval during differential transition Full-speed Source Electrical Characteristics Rise time (10 to 90%) Fall time (90 to 10%) Differential rise and fall time matching Full-speed data rate Frame interval Consecutive frame interval jitter Source jitter total (including frequency tolerance): To next transition For paired transitions Source jitter for differential transition to SE0 transition Receiver jitter: To next transition For paired transitions Source SE0 interval of EOP Receiver SE0 interval of EOP Width of SE0 interval during differential transition tJR1 tJR2 tFEOPT tFEOPR tFST -18.5 -9 160 82 14 +18.5 +9 175 ns ns ns ns ns tDJ1 tDJ2 tFDEOP -3.5 -4.0 -2 +3.5 +4.0 +5 ns ns ns tFR tFF tFRFM tFDRATHS tFRAME tRFI No clock adjustment CL = 50 pF, RS = 36 CL = 50 pF, RS = 36 (tFR/tFF) Average bit rate 90 11.9940 0.9995 111.11 12.0060 1.0005 42 % Mbps ms ns 4 20 ns 4 20 ns tUJR1 tUJR2 tLEOPT tLEOPR tFST -152 -200 1.25 670 210 +152 +200 1.50 ns ns tDDJ1 tDDJ2 tLDEOP -25 -14 -40 +25 +14 +100 ns ns ns tLR tLF tLRFM tLDRATHS CL = 200 to 600 pF, RS = 36 CL = 200 to 600 pF, RS = 36 (tLR/tLF) Average bit rate 80 1.49925 125 1.50075 % Mbps 75 300 ns 75 300 ns Symbol Conditions Min. Max. Unit
s
ns ns
Data Sheet S16265EJ4V0DS
23
PD720101
(2/2)
Parameter Symbol Conditions Min. Max. Unit High-speed Source Electrical Characteristics Rise time (10 to 90%) Fall time (90 to 10%) Driver waveform High-speed data rate Microframe interval Consecutive microframe interval difference Data source jitter Receiver jitter tolerance Hub Event Timings Time to detect a downstream facing port connect event Time to detect a disconnect event at a hub's downstream facing port Duration of driving resume to a downstream port Time from detecting downstream resume to rebroadcast Inter-packet delay for packets traveling in same direction for high-speed Inter-packet delay for packets traveling in opposite direction for high-speed Inter-packet delay for root hub response for high-speed Time for which a Chirp J or Chirp K must be continuously detected during reset handshake Time after end of device Chirp K by which hub must start driving first Chirp K Time for which each individual Chirp J or Chirp K in the chirp sequence is driven downstream during reset Time before end of reset by which a hub must end its downstream chirp sequence tDCHSE0 100 500 tDCHBIT 40 60 tWTDCH 100 tFILT 2.5 tHSRSPIPD1 192 tHSIPDOD 8 tHSIPDSD 88 Bit times Bit times Bit times tURSM 1.0 ms tDRSMDN Nominal 20 ms tDDIS 2.0 2.5 tDCNN 2.5 2000 tHSR tHSF See Figure 3-6. tHSDRAT tHSFRAM tHSRFI See Figure 3-6. See Figure 3-4. 479.760 124.9375 480.240 125.0625 4 highspeed Mbps 500 500 ps ps
s
Bit times
s s
s
s s
s
24
Data Sheet S16265EJ4V0DS
PD720101
Figure 3-6. Transmit Waveform for Transceiver at DP/DM
Level 1
Point 3 Point 4
+400 mV Differential
Point 1
Point 2
0V Differential
Point 5
Point 6
Level 2 Unit Interval 0% 100%
-400 mV Differential
Figure 3-7. Transmitter Measurement Fixtures
Test Supply Voltage 15.8 USB Connector Nearest Device Vbus D+ DGnd 50 Coax 50 Coax + To 50 Inputs of a High Speed Differential Oscilloscope, or 50 Outputs of a High Speed Differential Data Generator -
15.8
143
143
Data Sheet S16265EJ4V0DS
25
PD720101
3.4 Timing Diagram
PCI clock
tcyc
thigh
tlow
0.6VDD 0.5VDD 0.4VDD 0.3VDD 0.2VDD
0.4VDD (ptp:min)
PCI reset
PCLK 100 ms (typ.) PWR_GOOD trst-clk trst VBBRST0 trst-off PCI Signals Valid
26
Data Sheet S16265EJ4V0DS
PD720101
PCI output timing measurement condition
0.6VDD PCLK 0.4VDD tval , tval (ptp) 0.2VDD
0.615VDD (for falling edge) Output delay 0.285VDD (for falling edge)
Output
ton
toff
PCI input timing measurement condition
0.6VDD PCLK 0.4VDD 0.2VDD tsu , tsu (ptp) th 0.6VDD Input 0.4VDD 0.2VDD
Data Sheet S16265EJ4V0DS
27
PD720101
USB differential data jitter for full-speed
tPERIOD Differential Data Lines Crossover Points
Consecutive Transitions N x tPERIOD + txDJ1 Paired Transitions N x tPERIOD + txDJ2
USB differential-to-EOP transition skew and EOP width for low-/full-speed
tPERIOD Differential Data Lines Crossover Point Crossover Point Extended
Diff. Data-toSE0 Skew N x tPERIOD + txDEOP
Source EOP Width: tFEOPT tLEOPT Receiver EOP Width: tFEOPR tLEOPR
USB receiver jitter tolerance for low-/full-speed
tPERIOD Differential Data Lines
txJR
txJR1
txJR2
Consecutive Transitions N x tPERIOD + txJR1 Paired Transitions N x tPERIOD + txJR2
28
Data Sheet S16265EJ4V0DS
PD720101
Low-/full-speed disconnect detection
D+/D- VIZH (min)
VIL D-/D+ VSS tDDIS Device Disconnected Disconnect Detected
Full-/high-speed device connect detection
D+ VIH
D- VSS tDCNN Device Connected Connect Detected
Low-speed device connect detection
D- VIH
D+ VSS tDCNN Device Connected Connect Detected
Data Sheet S16265EJ4V0DS
29
PD720101
4. PACKAGE DRAWINGS
144-PIN PLASTIC LQFP (FINE PITCH) (20x20)
A B
108 109 73 72
detail of lead end
S C D R Q
144 1
37 36
F G H
I
M
J
P
K S L M
N
NOTE
S
Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 22.00.2 20.00.2 20.00.2 22.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.50.2 0.17 +0.03 -0.07 0.08 1.4 0.100.05 3 +4 -3 1.50.1 S144GJ-50-UEN
30
Data Sheet S16265EJ4V0DS
PD720101
144-PIN PLASTIC FBGA (12x12)
ZD E
wSB
ZE
B 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A D
INDEX MARK
wSA
P NM L K J HG F E D C B A
ITEM D E
MILLIMETERS 12.000.10 12.000.10 0.20 1.480.10 0.350.06 1.13 0.80 0.50 +0.05 -0.10 0.08 0.10 0.20 0.80 0.80 P144F1-80-EA8
A
y1 S
w A A1 A2
A2 S
e b
y
S
e
A1
S AB
x y y1 ZD ZE
b
x
M
Data Sheet S16265EJ4V0DS
31
PD720101
5. RECOMMENDED SOLDERING CONDITIONS
The PD720101 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
PD720101GJ-UEN: 144-pin plastic LQFP (Fine pitch) (20 x 20)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less Exposure limit: 3 days Partial heating
Note
Symbol IR35-103-3
(after that, prebake at 125C for 10 hours) -
Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
PD720101F1-EA8: 144-pin plastic FBGA (12 x 12)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less Exposure limit: 7 days
Note
Symbol IR35-107-3
(after that, prebake at 125C for 10 hours)
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
32
Data Sheet S16265EJ4V0DS
PD720101
[MEMO]
Data Sheet S16265EJ4V0DS
33
PD720101
[MEMO]
34
Data Sheet S16265EJ4V0DS
PD720101
NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions.
Purchase of NEC Electronics l2C components conveys a license under the Philips l2C Patent Rights to use these components in an l2C system, provided that the system conforms to the l2C Standard Specification as defined by Philips.
Data Sheet S16265EJ4V0DS
35
PD720101
USB logo is a trademark of USB Implementers Forum, Inc. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries.
* The information in this document is current as of June, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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